A Novel FPGA-Based LFSR PUF Design for IoT and Smart Applications
Document Type
Conference Proceeding
Publication Date
12-6-2018
Department
Computing
School
Computing Sciences and Computer Engineering
Abstract
Silicon Physical Unclonable Functions (SPUFs) are used for extracting unique and random binary signatures from semiconductor chips. This paper introduces the first asynchronous LFSR based PUF; namely, the LFSR-PUF, that can be specifically implemented on a FPGA. The proposed ALFSR-PUF is derived from an asynchronous LFSR that uses D-latch/flip-flops and LUTs on an FPGA to generate a random clock by exploiting the inherent manufacturing process variations of the design primitives. The LFSR-PUF efficiently uses FPGA basic building blocks in each CLB to optimally occupy a very small area (two slices) in the FPGA. Besides design efficiency and area optimization, the challenge-response space is also increased. Consequently, an instantiation of more than one PUF instance is possible within each CLB. Experimental results on Xilinx Spartan-3E FPGA (90 nm) show that the generated signatures are both unique and reliable under varying temperature and voltage conditions.
Publication Title
NAECON 2018-IEEE National Aerospace and Electronics Conference
Recommended Citation
Amsaad, F.,
Sherif, A.,
Dawoud, A.,
Niamat, M.,
Kose, S.
(2018). A Novel FPGA-Based LFSR PUF Design for IoT and Smart Applications. NAECON 2018-IEEE National Aerospace and Electronics Conference.
Available at: https://aquila.usm.edu/fac_pubs/15836